Posts Tagged ‘silicon’

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New Family of USB Power Delivery Controllers from Microchip

June 19, 2014

PR_UPD1001-7x5Finally Microchip announces the first device of a new family of USB Power Delivery Controllers, the UPD1001.

The new device is a highly flexible and configurable solution that supports the 5 USB-IF standard UPD power profiles plus an additional 25 UPD-compliant profiles for a total of 30 profiles supported by a single chip. This will allow designers to select the optimum power profiles in order to meet their specific application requirements.

Pro’s

  • Support 5 defined USBPD power profiles + 25 additional user’s defined profiles
  • Fully integrated. Microprocessor and USBPD controller
  • Offering integrated ADC for Voltage/current  monitoring
  • Coming with a ready-to-use UPD1001 Evaluation Kit (part # EVB-UPD100).  It integrates everything you need for a USB Power Delivery provider.
  • Delivered in Consumer (0°C to +70°C),  Industrial (-40°C to +85°C) and Automotive  (-40°C to +105°C) grade

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Con’s

  • Only provider, meaning not supporting  swap features. Looking at the published UPD100x family roadmap, we should wait for the UPD1002 to have the role swap available.
  • Compliant with USBPD v1.2. We are currently at v1.3
  • Not clear the level of flexibility and programmability

 

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Is the USB Power Delivery a Game Changer?

October 28, 2013

The first USB PD devices will come to market in 2014, with a “big roll-out” in 2015, says Brad Saunders of Intel. Gregory Reed, of the Swanson School of Engineering at the University of Pittsburgh, calls the new USB standard a “game-changer”.

This is an extract of an interesting article from The Economist related to the USB Power Delivery: The humble USB cable is part of an electrical revolution. It will make power supplies greener and cheaper.

Anyone interested on USB-PD and in general on new technology should read.

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Developing a USB Power Delivery device? Let’s talk about solutions!

July 1, 2013

Are you thinking to develop or evaluate an USB-PD device? If yes, I’m sure the first problem you are facing is the unavailability of USB-PD semiconductor solutions to build your concept board and of USB-PD enabled products to be used as peer for your system (at least at this date). This is for sure a major issue to assess the system requirements and to evaluate the performances. The possibility to have a USB-PD evaluation board permits the engineering team to start playing with this new protocol, to build the system and to start the implementation and debug of the high level functionalities.

Up to date two solutions are available in the market: one coming from Obsidian Technology and one from Canova Tech.

Everything I know about Obsidian can be found in the website. They came as first in the market with an USB-PD solution and they are offering an USB-PD development board  (OTS9102) based on a proprietary IC (OTI9121) implementing the physical layer (PHY).

CT20600

More I can say about Canova Tech (sorry, it’s the company I’m working for!). It’s currently developing an USB-PD PHY block, the CT20600.

The CT20600 is a USB-PD compliant PHY IP implementing all the features described in the current USB-PD specifications. The block can be integrated in a more complex power management unit (see previous post) or in standalone device for cost sensitive applications. The CT20600 can be ported to most of the analog CMOS processes available in the market.

CT20600 DVLP Board 1V1

A development board has been developed in order to assess the architecture and to implement the digital blocks of the PHY and the upper layers, like the protocol layer. Waiting for the incoming silicon samples, at the moment the board v1.1 implements the analog parts of the USB-PD PHY using discrete components and the digital blocks in a FPGA.

A detailed description of this board will follow soon.

Any comment and feedback is welcome.
Stay tuned.

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HowTo qualify an USB Power Delivery PHY

April 23, 2013

As far as I know, no USB Power Delivery products are available on the market and no standard or ASSP ICs can be found yet. Most  probably the major semiconductor companies are hard working to deliver soon solutions for this new standard and fabless semiconductor companies are ready to offer dedicated IP (e.g. CT20660 from Canova Tech).

USB EYEAs any USB product, compliance and interoperability tests should be performed in order to grant the requested level of compatibility with any compliant solution. The USB-IF defines a Compliance Program that provides reasonable measures of acceptability. Products that pass this level of acceptability are added to the Integrators List. You can check the  USB-IF Compliance Updates webpage for any news and update.

Two ways are available to have your product in this Integration List:

  1. participating in the USB-IF Sponsored Compliance Workshops
  2. contacting one of the Independent Test Labs.

Please check the USB.org website for more information.

Before submitting your products to compliance tests, it’s important and warmly encouraged by the USB-IF itself to run internally tests procedure to validate the solution. Normally the USB-IF delivers for any USB standard a list of test procedures and a test setup description to validate your design and debug it with a standard set of tests. This is very important and really crucial for new designs, especially in the case of a new USB standard without available alternative solutions to make comparisons and interoperability tests.

Unfortunately, up to day the USB-IF did not release yet the test procedures for the USB-PD delivery and there is no date for the delivery of such documentation.  See below the extract on the USB Power delivery page:

Compliance testing for products conforming to the Power Delivery Specification and the related Power Delivery icons are currently under development. More details to be added here later.”

Well, the USB-PD icon delivering is less important. Agreed.

I will continuously check the USB-IF webpage for any news and and I’m constantly  looking for any alternative and viable way to perform in-house preliminary compliance tests.

Keep tuned.

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Interview with S.Carlsen, commitee member for USB Power Delivery standardization

April 3, 2013

After my recent posts (USB-PD IntroPHYProtocol Layer) about USB Power Delivery, I had the chance to come in touch with great people and I started with them interesting and promising discussions. In the early phases of any new emerging technology it’s always important to build a wide network of  interest, competences and contributions.

Charger

In this sense, it is a pleasure to introduce Sten Carlsen, a member of the standardization committee of the USB-PD. Having covered this active role, Sten can help to better understand the new standard and read it out of the specification. Below the interview I had with him.

Read the rest of this entry ?

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USB-PD: Protocol Layer explained

March 27, 2013

After my previous post regarding the Power Delivery PHY, it’s now time to introduce the Protocol Layer (PL).USB-PD Stack PL

The PL communicates with the lower PHY layer and with the upper Policy Engine and it is responsible to form the messages used to communicate information between a pair of USB-PD ports.

It receives inputs from the Policy Engine indicating which messages to send and indicates the responses back to the Policy Engine. But it is responsible to  form Capabilities messages, requests and acknowledgements and ping packets. It implements counters for packet numbering and dedicated timer for timeouts.

The basic protocol uses a push model where the Provider pushes it capabilities to the Consumer that in turn responds with a request based on the offering. However, the Consumer may asynchronously request the Provider’s present capabilities and may select another voltage/current.

The PL architecture is based on timers, state machines and counters, see the picture, and it’s a pure digital implementation. Below a brief description of each block.

UBS-PD PL

Read the rest of this entry ?

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FinFET Technology for Dummies (like me)

March 20, 2013

finFET seems to be the most promising and disruptive technology at the moment able to mantain the Moore’s Law trend and expectations. The most active players (IDM, Foundries, EDA companies and IP providers) in the semiconductor market are putting a lot of effort, investments and emphasis on this hot topic.

For this reason I decided to collect information and share a post regarding this technology. It’s not anymore the time for me to enter in mathematical and physical details, but my interest  is to understand the reasons and the advantages of the FinFET technology from a marketing perspective.

Reasons

The Moore’s Law and the market are pushing constantly to increase the density of transistors in chip and the performances in term of speed and power consumption. This scaling process seems to be at a technology limit for the planar transistor with length below 20nm: the electrical parameters start degrading and the silicon process variations impact heavily in the performances. The main reason of this degradation is due to the planar structure itself: the gate does not have a good electrostatic field control away from the surface of the channel. With geometry scaling,  it brings to:

  • Lower current in the channel
  • Leakage current drain-source when the transistor is theoretically switched off 
  • Short channel effect
  • High dependence on process variations (Vth and swing).

Solution

The solution seems to be indeed the 3D approach:  the channel between source and drain is built as a three-dimensional bar on top of the silicon substrate, called fin. The gate electrode is then wrapped around the channel, so the gate can control the channel electrical field. In this structure, the gate can control much better the electrical field in the 3D channel.

Several options and enhancement are proposed. In the picture below a finFET has been built on SOI with a further reduction of current leakage. There can be formed several gate electrodes on each side which leads to reduced leakage effects and an enhanced drive current.

Advantages

FinFET technology impacts all the electrical parameters of the transistor and you have benefit in power consumption (static and dynamic), speed and voltage supply range. FinFETs also improve the always challenging tradeoff between performance and power: you can go faster with the same amount of power, compared to the planar equivalent, or save power at the same speed. In a list, the promised advantages over plan transistor:

  • Higher drain current
  • up to 37% switching speed
  • Lower switching voltage
  • less than half the dynamic power
  • 90% less static leakage current

The above points reached with a low cost impact: leading foundries estimate the additional processing cost of 3D devices to be 2% to 5% higher than that of the corresponding Planar wafer fabrication.

State of the Art

Almost all the big players in the semiconductor eco-system are focusing on the finFET technology, so news, announcements and updates come out every day.

The finFET era started  in 2011, when Intel unveiled the newfangled transistor technology at the 22nm node (now in production)Intel plans are to ramp up its second-generation finFET devices at 14nm by year’s end and move to 11nm by 2015.

Silicon Foundries are already defining their plans with finFETs technology. GlobalFoundries will deliver14nm finFET by 2014 and 10nm finFet by 2015. TSMC is planning to deliver 16nm finFET by 2014.

EDA player are dedicating big effort to model this complex device and to deliver compelling design tools to designers. In particular Synopsys is working hard to deliver tools and IP for FinFET design, as in the news.

Conclusion

Maybe we are at the beginning of a new era. finFETs can potentially determinate a big step forward in the never ending effort to reduce power consumption, to increase switching speed and number of transistors. Always with a cost reduction.