Archive for July, 2013

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USB Power Delivery Showcase from INTEL

July 11, 2013

At the Technology Showcase at IDF Beijing, INTEL demonstrated a typical application of the USB Power Delivery feature: a portable PC delivering through a USB2.0 connection video streaming at 480Mbit/s (not really a big deal) and at the same time the power to supply a LCD monitor.

INTEL DEMO@IDF

Read the rest of this entry ?

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New USB Power Delivery Specifications

July 4, 2013

New USB Power Delivery Specification (Rev. 1.0, Version 1.2, Including Errata through June 26, 2013) has been just released. Check it out.

More details will follow.

Andrea

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Developing a USB Power Delivery device? Let’s talk about solutions!

July 1, 2013

Are you thinking to develop or evaluate an USB-PD device? If yes, I’m sure the first problem you are facing is the unavailability of USB-PD semiconductor solutions to build your concept board and of USB-PD enabled products to be used as peer for your system (at least at this date). This is for sure a major issue to assess the system requirements and to evaluate the performances. The possibility to have a USB-PD evaluation board permits the engineering team to start playing with this new protocol, to build the system and to start the implementation and debug of the high level functionalities.

Up to date two solutions are available in the market: one coming from Obsidian Technology and one from Canova Tech.

Everything I know about Obsidian can be found in the website. They came as first in the market with an USB-PD solution and they are offering an USB-PD development board  (OTS9102) based on a proprietary IC (OTI9121) implementing the physical layer (PHY).

CT20600

More I can say about Canova Tech (sorry, it’s the company I’m working for!). It’s currently developing an USB-PD PHY block, the CT20600.

The CT20600 is a USB-PD compliant PHY IP implementing all the features described in the current USB-PD specifications. The block can be integrated in a more complex power management unit (see previous post) or in standalone device for cost sensitive applications. The CT20600 can be ported to most of the analog CMOS processes available in the market.

CT20600 DVLP Board 1V1

A development board has been developed in order to assess the architecture and to implement the digital blocks of the PHY and the upper layers, like the protocol layer. Waiting for the incoming silicon samples, at the moment the board v1.1 implements the analog parts of the USB-PD PHY using discrete components and the digital blocks in a FPGA.

A detailed description of this board will follow soon.

Any comment and feedback is welcome.
Stay tuned.