Archive for March, 2013

h1

USB-PD: Protocol Layer explained

March 27, 2013

After my previous post regarding the Power Delivery PHY, it’s now time to introduce the Protocol Layer (PL).USB-PD Stack PL

The PL communicates with the lower PHY layer and with the upper Policy Engine and it is responsible to form the messages used to communicate information between a pair of USB-PD ports.

It receives inputs from the Policy Engine indicating which messages to send and indicates the responses back to the Policy Engine. But it is responsible to  form Capabilities messages, requests and acknowledgements and ping packets. It implements counters for packet numbering and dedicated timer for timeouts.

The basic protocol uses a push model where the Provider pushes it capabilities to the Consumer that in turn responds with a request based on the offering. However, the Consumer may asynchronously request the Provider’s present capabilities and may select another voltage/current.

The PL architecture is based on timers, state machines and counters, see the picture, and it’s a pure digital implementation. Below a brief description of each block.

UBS-PD PL

Read the rest of this entry ?

h1

FinFET Technology for Dummies (like me)

March 20, 2013

finFET seems to be the most promising and disruptive technology at the moment able to mantain the Moore’s Law trend and expectations. The most active players (IDM, Foundries, EDA companies and IP providers) in the semiconductor market are putting a lot of effort, investments and emphasis on this hot topic.

For this reason I decided to collect information and share a post regarding this technology. It’s not anymore the time for me to enter in mathematical and physical details, but my interest  is to understand the reasons and the advantages of the FinFET technology from a marketing perspective.

Reasons

The Moore’s Law and the market are pushing constantly to increase the density of transistors in chip and the performances in term of speed and power consumption. This scaling process seems to be at a technology limit for the planar transistor with length below 20nm: the electrical parameters start degrading and the silicon process variations impact heavily in the performances. The main reason of this degradation is due to the planar structure itself: the gate does not have a good electrostatic field control away from the surface of the channel. With geometry scaling,  it brings to:

  • Lower current in the channel
  • Leakage current drain-source when the transistor is theoretically switched off 
  • Short channel effect
  • High dependence on process variations (Vth and swing).

Solution

The solution seems to be indeed the 3D approach:  the channel between source and drain is built as a three-dimensional bar on top of the silicon substrate, called fin. The gate electrode is then wrapped around the channel, so the gate can control the channel electrical field. In this structure, the gate can control much better the electrical field in the 3D channel.

Several options and enhancement are proposed. In the picture below a finFET has been built on SOI with a further reduction of current leakage. There can be formed several gate electrodes on each side which leads to reduced leakage effects and an enhanced drive current.

Advantages

FinFET technology impacts all the electrical parameters of the transistor and you have benefit in power consumption (static and dynamic), speed and voltage supply range. FinFETs also improve the always challenging tradeoff between performance and power: you can go faster with the same amount of power, compared to the planar equivalent, or save power at the same speed. In a list, the promised advantages over plan transistor:

  • Higher drain current
  • up to 37% switching speed
  • Lower switching voltage
  • less than half the dynamic power
  • 90% less static leakage current

The above points reached with a low cost impact: leading foundries estimate the additional processing cost of 3D devices to be 2% to 5% higher than that of the corresponding Planar wafer fabrication.

State of the Art

Almost all the big players in the semiconductor eco-system are focusing on the finFET technology, so news, announcements and updates come out every day.

The finFET era started  in 2011, when Intel unveiled the newfangled transistor technology at the 22nm node (now in production)Intel plans are to ramp up its second-generation finFET devices at 14nm by year’s end and move to 11nm by 2015.

Silicon Foundries are already defining their plans with finFETs technology. GlobalFoundries will deliver14nm finFET by 2014 and 10nm finFet by 2015. TSMC is planning to deliver 16nm finFET by 2014.

EDA player are dedicating big effort to model this complex device and to deliver compelling design tools to designers. In particular Synopsys is working hard to deliver tools and IP for FinFET design, as in the news.

Conclusion

Maybe we are at the beginning of a new era. finFETs can potentially determinate a big step forward in the never ending effort to reduce power consumption, to increase switching speed and number of transistors. Always with a cost reduction.

h1

USB Power Delivery: PHY explained

March 14, 2013

USB-PD iconsThe new USB Power Delivery standard (USB-PD) will enable devices to deliver or sink power  over USB cable up to 100W in 6 power profiles.  And hopefully it will simplify our life, currently busy with power adapters, battery chargers and connectors. In a previous post of mine, the main features of the USB-PD have been presented.

The USB-PD defines a protocol that enable the producer and the consumer device to negotiate the power capabilities and to tailor dinamically the actual power needs. To be compatible with the classic standard USB2.0 and USB3.0, this communication protocol has been specified as a powerline communication (PLC) over VBUS, as depicted in a simplified architecture below. In this configuration the USB-PD PHY in not interfering with the standard communication bus of a USB port and in principle nothing is preventing to have a separate and standalone USB-PD device.
usb-pd architecture

The USB-PD communication protocol is an half-duplex, FSK modulated channel. The frequency carrier is 23.2MHz and the FSK frequency deviation 500KHz. The bit rate is 300 Kbps.

The USB-PD PHY interfaces the VBUS wire only. An inductor is required to isolate the transceiver and the channel from the noisy power supply or load.

The USB-PD standard Specification doesn’t enter in implementation details, but I believe the most probable implementation will use an AC coupling with the VBUS, as depicted above. This approach permits to use low voltage silicon voltage processes, as the capacitor blocks the DC component of the VBUS that can be as high as 20V nominal.

In the above architecture, no mention of the standard USB interface, that it completely separated and independent. It will be interesting to investigate in another post how to protect the VBUS input in case of USB-PD functionality.

USB-PD PHY (TX)

The TX block receives data to be sent from the upper layer (protocol layer). The functions to be implemented are:
  1. Receive incoming data from upper layer
  2. Append the calculated CRC
  3. 4b5b encode to avoid DC component in the data stream
  4. Insert  preamble and packet delimiters
  5. FSK Modulator
  6. VUSB Drive with a bandpass filter

usb-pd tx

Without enter in implementation details, part of the TX block involves pure digital design. It will be interesting to investigate the implementation of the FSK modulator. The 4b5b encoder avoids DC component in the data stream. The  preamble makes the clock synchronization easier and the packet delimiters make the packet sync easier at the RX side.

USB-PD PHY RX

The RX block should receive data on the VBUS and send the payload data to the upper layer (protocol layer). The functions to be implemented are:
  1. PassBand Filter
  2. Squelch Detector
  3. FSK Demodulator
  4. Extract payload
  5. 4b5b Decoder
  6. CRC check
  7. Data to upper layer

usb-pd rx

The most interesting part of the RX is the FSK demodulator, as there are many alternative implementations. A coming post will be dedicated to this topic.

The RX squelch detector is requested to minimize the power consumption of the RX block when no data communication on VBUS. The CRC calculation and validation permits to discharge corrupted packets. Only bit-wise correct packet will be delivered to the upper layer (protocol layer).

h1

Ready for USB Power Delivery?

March 12, 2013

The USB promoter groups released on July 2012 the new Power Delivery 1.0 specifications for USB3.0 and USB2.0. This new profile defines the mechanisms to deliver flexible and higher power over  a standard USB data channel. USB Power Delivery (PD) devices can now delivery up to 100W and implement  power management strategies across multiple peripherals by allowing each device to take only the power it requires, and to get more power when required for a given application.

USB-PD icons

Compatible with the actual mechanical (cables and plugs) and protocol ecosystem and in addition to the current BC1.2 specifications(USB Battery Charge v1.2),  the new PD defines new cables and plug/sockets able to manage this higher power. The PD negotiation between devices is performed by a new specific communication protocol over the VBUS one-wire channel, without interfering with the USB data channel.

USB-PD Profiles

Compared with Thunderbolt, that is offering higher data speed performances, the USB PD specify a power delivery ten times what Thunderbolt can do. It means that you can charge up your laptop or power most any peripheral via Universal Serial Bus.
The natural implementation of this new PD profile is the wall plug charger that can now be used to deliver after negotiation enough power to supply and charge notebooks and portable devices. But any USB device with enough power capabilities, like a PD-enabled monitor, can be the USB power hub for multiple external devices like HDD/SDDs and notebook, as in picture below.

USB-PD Ecosystem

The new USB PD profile is a promising effort to unify and standardize the common needs of power delivery and to simplify the number and typologies of power cables we are now managing to charge and supply our battery operated devices.

h1

1st Post

March 11, 2013

primi passi   

   I don’t know if there’s the right way to start a  blog.

   I don’t know  howto  create a great blog.

   I don’t even  know  if I have something special to write.

   

  … Sometime it’s better to start with the first step.